This invention relates to circuit arrangements which can be implemented as integrated circuits that include what will be termed an "array logic structure".
For the purposes of the present specification an "array logic structure" is heredefined as a plurality of controllable insulated gate field effect transistors which are formed at selected intersections of an array consisting of a plurality of rows of series-connected gate regions and a plurality of columns of surface regions which at each selected intersection define source and drain regions for the transistor which is formed there, an electrical path being formed at each other (non-selected) intersection, at least in use of the structure, to effectively short circuit the intersection with respect to the relevant surface region column.
In one known form of this array logic structure, the controllable transistors at the selected intersections are formed as n-channel IGFETS of the enchancement type, and at the non-selected intersections there are formed n-channel IGFETS of the depletion type to provide the electrical paths which short-circuit (or bridge) these latter intersections in the direction of the relevant surface region column. Further information concerning such an array logic structure can be found in our United Kingdom patent specification No. 1,575,741, which corresponds to U.S. Pat. No. 4,336,452.
An array logic structure as defined above can be used to implement so-called combinatorial logic circuits (that is, circuits which can perform combinations of logic functions such as AND and OR functions) which are for use synchronously with dynamic circuits and which can be implemented in the same integrated circuit structure as the dynamic circuits. A known dynamic circuit which can be used as a binary stage for a known construction of binary counter is a two-phase dynamic D-type flip-flop. A plurality of these flip-flops are interconnected using synchronous combinatorial logic circuits implemented in an array logic structure to form the counter. However, the size of array logic structure which is necessary for the combinatorial logic circuits that are required to interconnect the flip-flops to form a counter having more than four stages, is so large as to be wasteful of chip area. Furthermore, these logic circuits may be unacceptably slow in operation because of the size of the structure. In fact, the size of the array logic structure increases non-linearly as the number of counter stages increases, so that this drawback increases in severity with increase in counter size.
In view of this drawback, it has hitherto been the practice, when a bit count is required whiqh is greater than that provided by such a binary counter having four stages, to use instead a pseudorandom ring counter whose stages are also formed by the known two-phase dynamic D-type flip-flops which are appropriately interconnected by combinatorial logic circuits. The normal maximum count of a pseudo-random ring counter is (2.sup.n -1), where n is the number of counter stages, and the counting sequence is not a natural binary counting sequence. The combinatorial logic circuits required for a pseudo-random ring counter which provides a given maximum count are far simpler than the combinatorial logic circuits required for a conventional binary counter which provides an equivalent maximum natural binary count. Therefore, when large bit counts are required, the use of an array logic structure to form the combinatorial logic circuits required for a pseudo-random ring counter can become acceptable as regards both chip area and operating speed.
However, in digital data systems, there are occasions when a natural binary counting sequence is essential, or at least desirable, for instance, when interfacing different equipments for the mutual transfer of data between them. If different binary counting sequences are used in such equipment, then translation of data transferred from one equipment to another may become necessary.